Traditionally, local ESD clamping devices are present in driver circuits to provide ESD discharge paths, for instance, from input/output (I/O) (or data) pads to a supply ground, from a power supply to a supply ground, etc. Individual clamping devices, however, typically require wide metal buses since these ESD clamping devices may need to discharge a large amount of ESD current (e.g., as high as 4 amps (A)), and wider metal buses reduce the voltage drop in power rails. Thus, the traditional approach generally results in a substantial amount of chip area consumed by ESD clamping devices, increased off-state leakage, etc.
FIG. 1 schematically illustrates one alternative to circuits with ESD clamping devices requiring wide metal buses. As shown, the circuit in FIG. 1 includes a number of data I/O cells 101 and power cells 103. Each data I/O cell 101 includes I/O pad 105, ESD clamping device 107, and diodes 109. Each power cell 103 includes trigger circuit 111 and transistor 113. Data I/O cells 101 are connected to each other and power cells 103 via power rail 115, trigger rail 117, and ground rail 119 with resistance 121 along the rails 115, 117, and 119. When an ESD event occurs, for instance, at one of the I/O pads 105, the trigger circuit 111 generates a trigger signal to all of the data I/O cells 101 to keep ESD clamping devices 107 on during the ESD event. Because ESD clamping devices 107 are distributed throughout each data I/O cell 101, and ESD current from the ESD event may travel to ground rail 119 through any of these ESD clamping devices 107, the amount of ESD current that each ESD clamping device 107 must carry is reduced, decreasing the size requirement with respect to the width of the metal buses. Nonetheless, the circuit in FIG. 1 requires closely-spaced ESD clamping devices 107 (e.g., the circuit therefore utilizes an ESD clamping device 107 in every data I/O cell 101), and, thus, still requires large areas for ESD clamping devices.
A need therefore exists for an effective ESD solution without sacrificing a substantial amount of chip area (e.g., for ESD clamping devices), and enabling methodology.